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Macros | |
| #define | CAT(a, b) CAT_(a, b) |
| #define | CAT_(a, b) a##b |
| #define | MOTOR_IO(n, t) CAT(M, CAT(n, t)) |
| #define | mn_has_limit(a) |
| #define | mn_has_home(a) |
| #define | mn_has_limit_max(a) |
| #define | mn_has_fault(a) |
| #define | mn_has_enable(a) |
| #define | N_MOTORS (3 + defined(M3_AVAILABLE) + defined(M4_AVAILABLE) + defined(M5_AVAILABLE) + defined(M6_AVAILABLE) + defined(M7_AVAILABLE)) |
| #define | HOME2_MASK 0 |
| #define | HOME2_MASK_SUM 0 |
| #define | MOTOR_FAULT2_MASK 0 |
| #define | MOTOR_FAULT2_MASK_SUM 0 |
| #define | LIMIT2_MASK 0 |
| #define | LIMIT2_MASK_SUM 0 |
| #define | X_STEP_BIT (1<<X_STEP_PIN) |
| #define | Y_STEP_BIT (1<<Y_STEP_PIN) |
| #define | Z_STEP_BIT (1<<Z_STEP_PIN) |
| #define | X_DIRECTION_BIT (1<<X_DIRECTION_PIN) |
| #define | Y_DIRECTION_BIT (1<<Y_DIRECTION_PIN) |
| #define | Z_DIRECTION_BIT (1<<Z_DIRECTION_PIN) |
| #define | X_HOME_BIT 0 |
| #define | Y_HOME_BIT 0 |
| #define | Z_HOME_BIT 0 |
| #define | X_MOTOR_FAULT_BIT 0 |
| #define | Y_MOTOR_FAULT_BIT 0 |
| #define | Z_MOTOR_FAULT_BIT 0 |
| #define | X_LIMIT_BIT (1<<X_LIMIT_PIN) |
| #define | Y_LIMIT_BIT (1<<Y_LIMIT_PIN) |
| #define | Z_LIMIT_BIT (1<<Z_LIMIT_PIN) |
| #define | X_LIMIT_MAX_BIT 0 |
| #define | Y_LIMIT_MAX_BIT 0 |
| #define | Z_LIMIT_MAX_BIT 0 |
| #define | LIMIT_MAX_MASK_BASE (X_LIMIT_MAX_BIT|Y_LIMIT_MAX_BIT|Z_LIMIT_MAX_BIT) |
| #define | LIMIT_MAX_MASK_BASE_SUM (X_LIMIT_MAX_BIT+Y_LIMIT_MAX_BIT+Z_LIMIT_MAX_BIT) |
| #define | LIMIT_MAX_MASK (LIMIT_MAX_MASK_BASE|M3_LIMIT_MAX_BIT|M4_LIMIT_MAX_BIT|M5_LIMIT_MAX_BIT|M6_LIMIT_MAX_BIT|M7_LIMIT_MAX_BIT) |
| #define | LIMIT_MAX_MASK_SUM (LIMIT_MAX_MASK_BASE_SUM+M3_LIMIT_MAX_BIT+M4_LIMIT_MAX_BIT+M5_LIMIT_MAX_BIT+M6_LIMIT_MAX_BIT+M7_LIMIT_MAX_BIT) |
| #define | STEP_MASK (X_STEP_BIT|Y_STEP_BIT|Z_STEP_BIT|M3_STEP_BIT|M4_STEP_BIT|M5_STEP_BIT|M6_STEP_BIT|M7_STEP_BIT) |
| #define | DIRECTION_MASK (X_DIRECTION_BIT|Y_DIRECTION_BIT|Z_DIRECTION_BIT|M3_DIRECTION_BIT|M4_DIRECTION_BIT|M5_DIRECTION_BIT|M6_DIRECTION_BIT|M7_DIRECTION_BIT) |
| #define | STEPPERS_ENABLE_MASK (X_ENABLE_BIT|Y_ENABLE_BIT|Z_ENABLE_BIT|M3_ENABLE_BIT|M4_ENABLE_BIT|M5_ENABLE_BIT|M6_ENABLE_BIT|M7_ENABLE_BIT) |
| #define | HOME_MASK_BASE (X_HOME_BIT|Y_HOME_BIT|Z_HOME_BIT|HOME2_MASK) |
| #define | HOME_MASK_BASE_SUM (X_HOME_BIT+Y_HOME_BIT+Z_HOME_BIT+HOME2_MASK_SUM) |
| #define | HOME_MASK (HOME_MASK_BASE|M3_HOME_BIT|M4_HOME_BIT|M5_HOME_BIT|M6_HOME_BIT|M7_HOME_BIT) |
| #define | HOME_MASK_SUM (HOME_MASK_BASE_SUM+M3_HOME_BIT+M4_HOME_BIT+M5_HOME_BIT+M6_HOME_BIT+M7_HOME_BIT) |
| #define | LIMIT_MASK_BASE (X_LIMIT_BIT|Y_LIMIT_BIT|Z_LIMIT_BIT|LIMIT2_MASK|LIMIT_MAX_MASK) |
| #define | LIMIT_MASK_BASE_SUM (X_LIMIT_BIT+Y_LIMIT_BIT+Z_LIMIT_BIT+LIMIT2_MASK_SUM+LIMIT_MAX_MASK_SUM) |
| #define | LIMIT_MASK (LIMIT_MASK_BASE|M3_LIMIT_BIT|M4_LIMIT_BIT|M5_LIMIT_BIT|M6_LIMIT_BIT|M7_LIMIT_BIT) |
| #define | LIMIT_MASK_SUM (LIMIT_MASK_BASE_SUM+M3_LIMIT_BIT+M4_LIMIT_BIT+M5_LIMIT_BIT+M6_LIMIT_BIT+M7_LIMIT_BIT) |
| #define | MOTOR_FAULT_MASK_BASE (X_MOTOR_FAULT_BIT|Y_MOTOR_FAULT_BIT|Z_MOTOR_FAULT_BIT|MOTOR_FAULT2_MASK) |
| #define | MOTOR_FAULT_MASK_BASE_SUM (X_MOTOR_FAULT_BIT+Y_MOTOR_FAULT_BIT+Z_MOTOR_FAULT_BIT+MOTOR_FAULT2_MASK_SUM) |
| #define | MOTOR_FAULT_MASK (MOTOR_FAULT_MASK_BASE|M3_MOTOR_FAULT_BIT|M4_MOTOR_FAULT_BIT|M5_MOTOR_FAULT_BIT|M6_MOTOR_FAULT_BIT|M7_MOTOR_FAULT_BIT) |
| #define | MOTOR_FAULT_MASK_SUM (MOTOR_FAULT_MASK_BASE_SUM+M3_MOTOR_FAULT_BIT+M4_MOTOR_FAULT_BIT+M5_MOTOR_FAULT_BIT+M6_MOTOR_FAULT_BIT+M7_MOTOR_FAULT_BIT) |
| #define | N_GANGED 0 |
| #define CAT | ( | a, | |
| b | |||
| ) | CAT_(a, b) |
| #define CAT_ | ( | a, | |
| b | |||
| ) | a##b |
| #define DIRECTION_MASK (X_DIRECTION_BIT|Y_DIRECTION_BIT|Z_DIRECTION_BIT|M3_DIRECTION_BIT|M4_DIRECTION_BIT|M5_DIRECTION_BIT|M6_DIRECTION_BIT|M7_DIRECTION_BIT) |
| #define HOME2_MASK 0 |
| #define HOME2_MASK_SUM 0 |
| #define HOME_MASK (HOME_MASK_BASE|M3_HOME_BIT|M4_HOME_BIT|M5_HOME_BIT|M6_HOME_BIT|M7_HOME_BIT) |
| #define HOME_MASK_BASE (X_HOME_BIT|Y_HOME_BIT|Z_HOME_BIT|HOME2_MASK) |
| #define HOME_MASK_BASE_SUM (X_HOME_BIT+Y_HOME_BIT+Z_HOME_BIT+HOME2_MASK_SUM) |
| #define HOME_MASK_SUM (HOME_MASK_BASE_SUM+M3_HOME_BIT+M4_HOME_BIT+M5_HOME_BIT+M6_HOME_BIT+M7_HOME_BIT) |
| #define LIMIT2_MASK 0 |
| #define LIMIT2_MASK_SUM 0 |
| #define LIMIT_MASK (LIMIT_MASK_BASE|M3_LIMIT_BIT|M4_LIMIT_BIT|M5_LIMIT_BIT|M6_LIMIT_BIT|M7_LIMIT_BIT) |
| #define LIMIT_MASK_BASE (X_LIMIT_BIT|Y_LIMIT_BIT|Z_LIMIT_BIT|LIMIT2_MASK|LIMIT_MAX_MASK) |
| #define LIMIT_MASK_BASE_SUM (X_LIMIT_BIT+Y_LIMIT_BIT+Z_LIMIT_BIT+LIMIT2_MASK_SUM+LIMIT_MAX_MASK_SUM) |
| #define LIMIT_MASK_SUM (LIMIT_MASK_BASE_SUM+M3_LIMIT_BIT+M4_LIMIT_BIT+M5_LIMIT_BIT+M6_LIMIT_BIT+M7_LIMIT_BIT) |
| #define LIMIT_MAX_MASK (LIMIT_MAX_MASK_BASE|M3_LIMIT_MAX_BIT|M4_LIMIT_MAX_BIT|M5_LIMIT_MAX_BIT|M6_LIMIT_MAX_BIT|M7_LIMIT_MAX_BIT) |
| #define LIMIT_MAX_MASK_BASE (X_LIMIT_MAX_BIT|Y_LIMIT_MAX_BIT|Z_LIMIT_MAX_BIT) |
| #define LIMIT_MAX_MASK_BASE_SUM (X_LIMIT_MAX_BIT+Y_LIMIT_MAX_BIT+Z_LIMIT_MAX_BIT) |
| #define LIMIT_MAX_MASK_SUM (LIMIT_MAX_MASK_BASE_SUM+M3_LIMIT_MAX_BIT+M4_LIMIT_MAX_BIT+M5_LIMIT_MAX_BIT+M6_LIMIT_MAX_BIT+M7_LIMIT_MAX_BIT) |
| #define mn_has_enable | ( | a | ) |
| #define mn_has_fault | ( | a | ) |
| #define mn_has_home | ( | a | ) |
| #define mn_has_limit | ( | a | ) |
| #define mn_has_limit_max | ( | a | ) |
| #define MOTOR_FAULT2_MASK 0 |
| #define MOTOR_FAULT2_MASK_SUM 0 |
| #define MOTOR_FAULT_MASK (MOTOR_FAULT_MASK_BASE|M3_MOTOR_FAULT_BIT|M4_MOTOR_FAULT_BIT|M5_MOTOR_FAULT_BIT|M6_MOTOR_FAULT_BIT|M7_MOTOR_FAULT_BIT) |
| #define MOTOR_FAULT_MASK_BASE (X_MOTOR_FAULT_BIT|Y_MOTOR_FAULT_BIT|Z_MOTOR_FAULT_BIT|MOTOR_FAULT2_MASK) |
| #define MOTOR_FAULT_MASK_BASE_SUM (X_MOTOR_FAULT_BIT+Y_MOTOR_FAULT_BIT+Z_MOTOR_FAULT_BIT+MOTOR_FAULT2_MASK_SUM) |
| #define MOTOR_FAULT_MASK_SUM (MOTOR_FAULT_MASK_BASE_SUM+M3_MOTOR_FAULT_BIT+M4_MOTOR_FAULT_BIT+M5_MOTOR_FAULT_BIT+M6_MOTOR_FAULT_BIT+M7_MOTOR_FAULT_BIT) |
| #define N_GANGED 0 |
| #define N_MOTORS (3 + defined(M3_AVAILABLE) + defined(M4_AVAILABLE) + defined(M5_AVAILABLE) + defined(M6_AVAILABLE) + defined(M7_AVAILABLE)) |
| #define STEP_MASK (X_STEP_BIT|Y_STEP_BIT|Z_STEP_BIT|M3_STEP_BIT|M4_STEP_BIT|M5_STEP_BIT|M6_STEP_BIT|M7_STEP_BIT) |
| #define STEPPERS_ENABLE_MASK (X_ENABLE_BIT|Y_ENABLE_BIT|Z_ENABLE_BIT|M3_ENABLE_BIT|M4_ENABLE_BIT|M5_ENABLE_BIT|M6_ENABLE_BIT|M7_ENABLE_BIT) |
| #define X_DIRECTION_BIT (1<<X_DIRECTION_PIN) |
| #define X_HOME_BIT 0 |
| #define X_LIMIT_BIT (1<<X_LIMIT_PIN) |
| #define X_LIMIT_MAX_BIT 0 |
| #define X_MOTOR_FAULT_BIT 0 |
| #define X_STEP_BIT (1<<X_STEP_PIN) |
| #define Y_DIRECTION_BIT (1<<Y_DIRECTION_PIN) |
| #define Y_HOME_BIT 0 |
| #define Y_LIMIT_BIT (1<<Y_LIMIT_PIN) |
| #define Y_LIMIT_MAX_BIT 0 |
| #define Y_MOTOR_FAULT_BIT 0 |
| #define Y_STEP_BIT (1<<Y_STEP_PIN) |
| #define Z_DIRECTION_BIT (1<<Z_DIRECTION_PIN) |
| #define Z_HOME_BIT 0 |
| #define Z_LIMIT_BIT (1<<Z_LIMIT_PIN) |
| #define Z_LIMIT_MAX_BIT 0 |
| #define Z_MOTOR_FAULT_BIT 0 |
| #define Z_STEP_BIT (1<<Z_STEP_PIN) |